You are provisioning a server with eight-core 3 GHz CMP that can execute a workload with an overall CPI of 2.0 (assuming that L2 cache miss refills are not delayed). The L2 cache line size is 32 bytes. Assuming the system uses DDR2-667 DIMMs, how many independent memory channels should be provided so the system is not limited by memory bandwidth if the bandwidth required is sometimes twice the average

Question

Computers & Technology

Branson Donaldson

1 July, 00:21

You are provisioning a server with eight-core 3 GHz CMP that can execute a workload with an overall CPI of 2.0 (assuming that L2 cache miss refills are not delayed). The L2 cache line size is 32 bytes. Assuming the system uses DDR2-667 DIMMs, how many independent memory channels should be provided so the system is not limited by memory bandwidth if the bandwidth required is sometimes twice the average

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Abigayle Lester · Answer 1

The explanation for the question is given in the Explanation section below.

Explanation:

Throughout the query, we gave that we already have 8 core 3 GHz CMP and therefore it performs workflow in 2.0 CPI.

So,

(8 cores*3 GHz) / 2.0 CPI = 12 billion/second guidance, we've turned GHz into seconds, so that's a billion years.

Well into the question considering whether he loses 6.67 L2 per 1 K direction.

So,

12*0.00667 = 80 million mistakes per second level-2. For an 8, so 32B*80 = 2560 MB per sec.

Whether the maximum storage capacity is double that of high as 2560*2 = 5120 MB per sec.

However, that's just throughout the DDR2-67 DIMM range. So, we should infer this, because only one storage source could be enough.