What is meant by instruction pipelining in RISC processor? Whatare

' / the problems that may accompany this technology?

The instruction pipelining refers to various stages the instruction has to go through for the full execution of the instruction. Each instruction undergoes various stages in the execution, they are Instruction Fetch, Instruction Decode, Address Generator, Data Fetch, Execution and Write Back. Not every instruction may go through all the stages stated above. Pipelining exploits the parallelism in the execution of instructions (executing multiple instructions simultaneously). Each instruction might be at different stage in the execution of program. It can be a 3-stage pipelining or 5 stage pipelining.

The implementation of Pipelining is a complex procedure.

In branch instructions, the complexity increases with the number of stages of pipeline.